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Summary of Progress:
A radiation hardened memory and logic design using hybrid spintronic-CMOS devices has been proposed to develop under this project. The simulation of radiation hardened MRAM, radiation hardened magnetic full adder, and a fabrication of prototype MTJ are carried out in the current year that are briefly summarized as below: Radiation hardened MRAM: A simulation study of hybrid spintronic-CMOS circuit has been done in terms of its read energy as well as the effect of radiation on the memory operation has been analyzed. To develop a fast, energy efficient memory, spin transfer torque magnetic random-access memory (STT-MRAM) and spin orbit torque magnetic random-access memory (SOT-MRAM) has been simulated. However, STT-MRAM suffers from coupled read/write path, high write current and dielectric breakdown problems. Hence, to overcome these limitations SOT-MRAM has been analyzed in more depth. SOT-MTJ has been demonstrated to attain ultrafast and energy efficient switching because of its higher spin-torque efficiency. Furthermore, the decoupled read and write paths result in its improved endurance. SOT-based spintronic memory has provided a unique solution to address the endurance issue while ensuring better performance in power dissipation. A hybrid spintronic/CMOS circuit mainly includes the magnetic storage elements (e.g., MTJs) and the CMOS peripheral transistors. The MTJs are inherently robust against radiation particles because data stored in the MTJs are represented by the spin direction ‘up’ and ‘down’ of the electrons instead of electrical charges. However, the CMOS transistors make the whole circuit vulnerable to the radiation effect. The read circuit of the SOT-MRAM is vulnerable to single event upset (SEUs) and double node upset (DNUs). The hardening read circuit can recover these types of soft errors. When a radiation-induced particle strikes a sensitive node of a MOS transistor, electron–hole pairs are generated along its path with energy loss, which are separated by the electric field. These injected charges are accumulated at the drain, resulting in a radiation-induced current pulse. A model of a double-exponential current source is utilized to simulate particles hitting the sensitive nodes. The injected current source is described by the following equation:
I inj ( t ) =
Qinj
( e
− t /❑ 1
− e
− t /❑ 2
where ❑ 1 is the collection time constant for a junction (with a typical value of 150 ps) and ❑ 2 is
the ion track establishment time constant (with a typical value of 50 ps), Qinj is the amount of
injected charges, whose positive or negative sign (Fig.1) corresponds to whether the particle hits
an NMOS or a PMOS transistor, and the values of Qinj range from −2 to 2 pC.
The proposed novel 13T-radiation-hardened read circuit comprises of basic PCSA, four PMOS transistors (P5-P8), and two NMOS transistors (N4 and N5) as shown in Fig. 2 (a). Soft errors such as SEU and DNU can be recovered using the proposed radiation-hardened read circuit. The schematic of the simulated radiation hardened circuit, its transient response and the layout of the proposed circuit is shown in Fig 2-4.
(a) (b) Fig. 1. The circuit showing the polarity of the current to generate (a) a negative transient pulse at the '1' storing sensitive node (b) a positive transient pulse at the '0' storing sensitive node **0 10 20 30 40
Q (V) Time (ns) Qb (V) S**^1 (V) S^0 (V) Precharge SEN (V) Sensing (a) (b) Fig. 2 (a) Schematic of the proposed radiation hardened read circuit for the SOT-MRAM cell, and (b) Transient analysis of the proposed circuit without radiation effects. **0 10 20 30 40
-0.
Recovery Sensing Qb (V) Q (V) Time (ns) Recovery S**^1 (V) Recovery S^0 **(V) Precharge SEN (V)
-0.
0 2 4 6 8 10**
- - 0 2 4 charge^ Pre- Sensing SEN ( V ) S 1 S 0 Q recovery Qb recovery Voltage (V) DNU I (mA) Time (ns)
**0 10 20 30 40 50 60 70 80 90 100 -1.
-1.
-1.
1.**
- 0 **1
S Recovery @1000fC 0 Time (ns) Recovery @1000fC S**^1 SUM^ Recovery @1000fC C i^ B^ A Precharge phase Sensing phase SEN(V) (a) (b) Fig. 5. (a) The proposed radiation hardened magnetic full adder using the SOT-MRAM cell, (b) Transient simulation results of the proposed radiation-hardened MFA circuit in the presence of 1000 fC radiation particle. **0 1 2 3 4 5
1000 fC 200 fC S 1 recovery Sensing phase Precharge phase Time (ns) Voltage (V) 0 1 2 3 4 5 -1. -0.
1000 fC 200 fC S 0 recovery Voltage (V) Time (ns) phase Sensing phase Precharge -1.2 0 1 2 3 4 5 -0.
Precharge phase Sensing phase 1000 fC 200 fC SUM recovery Voltage (V) Time (ns)** (a) (b) (c) Fig. 6. Behaviour of soft-recovery with various values of Qinj from 200 fC to 1000 fC at (a) node S 1 , (b) node S 0 , and (c) node SUM. **0.
0 4 8 12 16 20
0 2 4 Pre-charge Sensing SEN (V)** SUM SUM S 0 recovery @1000fC S 1 recovery @1000fC Voltage (V) MNU @S 1 and S 0 Time (ns) I (mA) (a) (b) Fig. 7. Transient simulation waveform when the sensitive nodes are struck by MNU with 1000 fC radiation particle, (b) Layout of the proposed RH-MFA.
Fabrication of prototype MTJ device: The fabrication of the prototype MTJ of 10 μm ×10 μm has been done at the state-of-the-art laboratory at IIT Roorkee. The schematic of the fabricated device is shown in Fig. 8. Fig. 8 schematic of the fabricated device. The process flow of the MTJ fabrication is briefly summarized as below: Fabrication started with the oxidation of silicon (Si) wafer in the thermal furnace at 1100^0 C. A 200 nm thick film of SiO 2 is grown by standard oxidation recipe. The SiO 2 surface roughness as shown in Fig. 9(a) is measured by atomic force microscopy and found to be ∼0.5 nm (r.m.s), which confirms the smooth oxide/FL interface. A mask is developed using the laser writer as shown in Fig. 9 (b). Further Polymethylmethacrylate (PMMA) is used as a positive photoresist material. A thin layer of Pt (30 nm) employed as a bottom electrode, is deposited using DC sputtering and patterned using laser writer. Lift-off technique has been used to peel off the unwanted deposited materials. The optical image of the patterned bottom electrode is shown in Fig. 9 (c). To increase the adhesivity of Pt with SiO 2 , a 20 nm TaN is also deposited by RF sputtering that further followed by the deposition of CoFeB (2 nm)/MgO (1.8 nm)/CoFeB ( nm). Annealing at 370oC in a vacuum for 1 hour has been performed for optimum device operation to improve the crystalline property of deposited layer device. Later, a top electrode of TaN followed by Pt is deposited by DC sputtering. The Lift-off is achieved by dipping the sample in acetone for 2 minutes and sonicate for 3 minutes in acetone. After each lift-off, sample is blowed using N 2 gun to prevent coffee stains. An interlayer dielectric (ILD) of HfO 2 is deposited to prevent the short circuit of top and bottom electrode. In order to remove the undesired ring shapes while lift-off, a bilayer resist of MMA-MAA copolymer or EL 8.5 and PMMA is used. The successful fabrication of the tunnel junction is confirmed by the non- linearity in I-V curve measured by probe station as shown in Fig. 10. (a) (b)
We proposed a parallel DSHE (p-DSHE) and parallel SOT and STT based MRAM devices have been proposed to achieve high density, fast switching and low power consumption. These devices are 62% more area-efficient in comparison to SOT based 1-bit MRAM and show 97% and 59% reduction in energy and latency, respectively. As a result of the proposed model, the following benefits are achieved:
- The proposed FLCs have an improvement in terms of latency, energy, and area when compared to previous works related to multibit storage. Furthermore, the proposed FLCs offer 8% and 4% savings in read access energy and 87% and 13% savings in write access energy, respectively.
- The proposed FLC structures have a storage capacity of four bits with comparatively low power consumption and switching latency compared to conventional multibit MRAM cells. In our next article, we showed an energy-efficient solution for encryption in a non-volatile CiM architecture using a voltage-controlled SOT device. The voltage-controlled SOT-based RNG generates random keys for encryption and offers better throughput and area efficiency. The above article has some advantages as follows:
- The energy per random bit for the voltage-controlled SOT-based RNG is 3.31 fJ, and the throughput is 285 Mb/s. The voltage-controlled SOT-based RNG improves energy efficiency by more than 95% and 76%, respectively. We propose a model of hybrid CMOS/MTJ based AND/NAND, XOR/XNOR and full adder logic circuits with all-optical MTJ switching are presented. The proposed model yields the following benefits:
- The performance parameters of all optically switched (AOS)-MTJ are improved when compared with existing switching mechanisms such as STT and SOT. The energy efficiency of AOS-MTJ based NAND and XOR gates is increased by 88% and 12%, respectively, and the logic delay is improved by 97% and 91%. Spintronic devices based on antiferromagnetic skyrmion motion on the nanotracks have gained significant interest as a key component of neuromorphic data processing systems. The suggested device exhibits the leaky-integrate-fire functionality and achieves high-speed and energy-efficient devices in AFM spintronics for neuromorphic computing. This leads to the following benefits:
- The energy of skyrmions increases with increase in skyrmion-boundary interaction potential, but decreases with increase in distance between the core of the skyrmions and the tapered nanotrack edges.
- AFM skyrmion based shape-configured LIF neuron device is proposed by exploiting the tapered nano-tracks. It offers very fast processing speed and low energy consumption, making it an ideal candidate for the neuromorphic computing implementation.
Methodology:
Spintronics devices, especially hybrid spintronics/CMOS devices, are used as an emerging storage/logic technology that comprises of remarkable features such as nonvolatility, high power efficiency with almost zero static power loss, scalability, high density, and full compatibility of MTJs with CMOS technology. MTJ is the basic building component of such hybrid MTJ/CMOS design architecture. It is highly robust against the faults or errors that are caused due to radiation effects. However, hybrid MTJ/CMOS circuits are still susceptible to the radiation effect due to their peripheral CMOS based read circuit. MTJ devices are constituted of ferromagnetic materials such as CoFeB with magnetic properties that are not sensitive to radiation. Data is stored in the form of the direction of the magnetization and not conventionally in the form of an electric charge, which is an essential property for space applications. The integration of highly robust non-volatile spin-based components (such as MTJ) with CMOS counterparts could lead to new ways of data retention in harsh environments. Radiation hardened design techniques in conventional CMOS device technology is a widely researched topic, but it is still an unaddressed issue in hybrid MTJ/CMOS nonvolatile circuits. This necessitates for a solution to design hybrid MTJ/CMOS technology based reliable circuits that would be immune to the radiation effects. The approach of the project proposal is as follows:
- Literature survey of radiation hardened spintronics based circuits and further, to combine all the benefits by regrouping several design methods of microelectronic architecture responding to the shortcomings of radiation present environmental applications into a novel architecture.
- A complete circuit has to be created, designed, simulated and validated for radiation present environment. The approach of the project proposal is as follows:
- Literature Survey: Literature review of radiation-hardened spintronic-based circuits, with the goal to combine several microelectronic architecture design methods and address the challenge of radiation induced effects in present environmental applications.
- Design of Hybrid CMOS/MTJ radiation hardened MRAM cell: A radiation hardened MRAM is designed by using hybrid MTJ/CMOS scheme. The proposed design is implemented in 45nm CMOS technology node and the circuit is simulated and validated for radiation present environment and compared with the previous works for performance evaluation. The model parameters for CMOS peripheral circuitry and MTJ is investigated for our proposal to be executed efficiently.
- Radiation hardening of CMOS/MTJ based MRAM cell: A typical MRAM cell consists of two sensitive nodes. When a sufficient amount of charge is collected by these nodes, the output gets distorted. A transient fault is generated if the injected
Fig. 1 Magnetic Tunnel Junction Stack The purpose of different layers is given in the Table 1. Table 1 Purpose of different layers in MTJ stack MTJ Stack Layers (From Bottom) Purpose NiFeCr Magnetic buffer layer CoFe Bottom FM layer Magnetically oriented with annealing. Ru Antiferromagnetic coupling layer to top FM layer (CoFeB) in Synthetic Antiferromagnet (SAF) sandwich. CoFeB (Lower) Reference layer in MTJ which is pinned using SAF coupling. MgO Tunneling barrier in MTJ CoFeB (Upper) Free layer in MTJ Ru Capping layer for protecting. Annealing: The MTJ stacking structure will be annealed at 275°C for 1 hour in a 2.5-10 kOe magnetic field to obtain high TMR value. Large TMR ratios are achieved only after high temperature magnetic annealing of the samples. Thin Film Characterization: Surface characterization of deposited films will be done using X- ray diffraction technique. X-ray diffraction is a very accurate method for characterizing thin films. For our MTJ fabrication project, low angle XRD will be used extensively to probe the surface characteristics of our thin films as a function of the deposition parameters. Lithography: The already prepared MTJ will be patterned using lithography process and ion milling into a required shape and contact development. Testing: The fabricated MTJ will be used to implement the proposed radiation hardened MTJ/CMOS unit and tested for the radiation immunity at VECC Kolkata.
Work to be done under the project:
The project is in the final stage and all framework for the radiation hardened memory has been developed. The proposed novel memory design and logics (magnetic full adder) using hybrid CMOS-MTJ is examined for the radiation effects with a charge tolerant up to 1000 fC, which is
highest among the reported radiation hardened circuits. At the end of this financial year, we have completed all the targeted simulation and analytical work. But the fabrication of MTJ in state of art laboratory is still remain to be pending due to restrictions of CIVID-19 pandemic. The other research objectives of the project are being carried out in parallel. The status of the other objectives is discussed as following:
- Fabrication and testing of Magnetic Tunnel junction.
- Integration and design testing. MTJ fabrication in state-of-the-art laboratories is still pending due to limitations imposed by the COVID-19 pandemic, which have caused delays in the fabrication of the MTJ. Parallel research efforts are being conducted in order to achieve the other objectives of the project. As an overview of the status of the other objectives, we will discuss them as follows:
- Testing and fabricating a magnetic tunnel junction in order to determine its functionality.
- Testing of the integration process and the design process.
Suggestions for commercial application:
The ongoing project, utilized to design low power, nonvolatile and radiation hardened memory/logic circuits for space and military applications. Radiation hardened FPGA, microprocessors and microcontrollers using MRAM in the place of SRAM or Flash are currently under industrial development for aerospace and avionic applications. The present project has a wide window of opportunity for better MRAM integration for aerospace and avionic electronics which could become the orthodox solution in the future.
Any other scientific information:
Along with the significant work in the radiation-hardened memory and logic design, the project also focused on some other recent research areas such as antiferromagnetic skyrmion based neuron devices, energy-efficient advanced data encryption system using spin-based computing-in-memory architecture, SOT and STT based four-bit parallel MRAM cell for high-density applications and hybrid spintronics/CMOS logic circuits using all- optical-enabled MTJ. All the work is also published in the reputed journals.
