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summary of microelectronics all modules for nit durgapur electornicncs and comminucation e, Schemes and Mind Maps of Microelectronic Circuits

design using root locus PD controller 1/s(s+2) the specification given are overshoot 10% ,tp/ts= 1 sec

Typology: Schemes and Mind Maps

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Department of Electronics and Communication Engineering, NIT Durgapur
Course
Code
Title of the course Program Core
(PCR) /
Electives (PEL)
Total Number of contact hours Credit
Lecture
(L)
Tutorial
(T)
Practical
(P)
Total
Hours
ECC405/
ECS453
Microelectronics/
Analog Circuits/
Lab
CORE (PCR) 3 1 0 4 4
Pre-requisites:
ECC-01 (Basic Electronics);
Network Analysis with Good
understanding of RC Circuits.
Course Assessment methods:
1) Continuous Assessment (CA:15%) &
2) Mid-term (25 %), 3) End-term (60%))
Course
Outcomes
(CO)
CO1: Understand and analyze MOS characteristics, Short-channel effects, Sub-
threshold behavior.
CO2: Analyze Large/Small Signal MOS Circuits
CO3: Define frequency response, stability and compensation of Amplifiers
CO4: Evaluate specifications from a given design of OTA/OpAmp/OTA
CO5: Design of single stage OpAmp/OTA.
CO6: Concept of gm/ID and its applications in CMOS design.
Topics to be
Introduced Module 1: MOS transistor Structure, and IV characteristics [Large-signal, Sub-
threshold], Small signal model, Transconductance(s)[gm, gds, gmb]; MOS
Capacitances, High frequency small signal model, fT (ωT)
[7 hrs.]
Module 2: Common/Grounded {Source, Gate, Drain} amplifier, frequency response,
Miller effect.
[6 hrs.]
Module 3: Introduction to negative feedback; Closed loop behavior of First, Second
and Third-order systems in a feedback loop; Gain and Phase margin
[7 hrs]
Module 4: Dominant pole compensation; Pole splitting with Miller capacitance
[3 hrs.]
Module 5: Controlled sources using MOS transistors and OpAmps; Swing limits of
amplifiers;
[5 hrs.]
Module 6: MOS Current mirrors, Active load; CMOS inverter; Differential pair
[7 hrs.]
Module 7: Single stage and Two stage OpAmps; Specification Sheet; Miller
compensation.
[7 hrs.]
Module 7: Review of BJT, BJT in CMOS process, Intro to FinFET
[3 hrs]
Text Books,
and/or
reference
materials
Text / Reference Books:
[1] Design of Analog CMOS Integrated Circuits, by Behzad Razavi, McGraw-Hill, 2014.
B. TECH.(UG) IN ELECTRONICS & COMMUNICATION ENGINEERING
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Department of Electronics and Communication Engineering, NIT Durgapur Course Code

Title of the course Program Core (PCR) / Electives (PEL)

Total Number of contact hours Credit Lecture (L)

Tutorial (T)

Practical (P)

Total Hours ECC405 / ECS

Microelectronics / Analog Circuits/ Lab

CORE (PCR) 3 1 0 4 4

Pre-requisites: ECC-01 (Basic Electronics); Network Analysis with Good understanding of RC Circuits.

Course Assessment methods :

  1. Continuous Assessment (CA:15%) &
  2. Mid-term (25 %), 3) End-term (60%))

Course Outcomes (CO)

CO1: Understand and analyze MOS characteristics, Short-channel effects, Sub- threshold behavior.  CO2: Analyze Large/Small Signal MOS Circuits  CO3: Define frequency response, stability and compensation of AmplifiersCO4: Evaluate specifications from a given design of OTA/OpAmp/OTACO5: Design of single stage OpAmp/OTA.  CO6: Concept of g (^) m/I (^) D and its applications in CMOS design. Topics to be Introduced Module 1: MOS transistor Structure, and IV characteristics [Large-signal, Sub- threshold], Small signal model, Transconductance(s)[gm, g (^) ds, g (^) mb]; MOS Capacitances, High frequency small signal model, fT (ωT ) [7 hrs.] Module 2: Common/Grounded {Source, Gate, Drain} amplifier, frequency response, Miller effect. [6 hrs.] Module 3: Introduction to negative feedback; Closed loop behavior of First, Second and Third-order systems in a feedback loop; Gain and Phase margin [7 hrs] Module 4: Dominant pole compensation; Pole splitting with Miller capacitance [3 hrs.] Module 5: Controlled sources using MOS transistors and OpAmps; Swing limits of amplifiers; [5 hrs.] Module 6: MOS Current mirrors, Active load; CMOS inverter; Differential pair [7 hrs.] Module 7: Single stage and Two stage OpAmps; Specification Sheet; Miller compensation. [7 hrs.] Module 7: Review of BJT, BJT in CMOS process, Intro to FinFET [3 hrs] Text Books, and/or reference materials

Text / Reference Books:

[1] Design of Analog CMOS Integrated Circuits, by Behzad Razavi, McGraw-Hill, 2014.

B. TECH.(UG) IN ELECTRONICS & COMMUNICATION ENGINEERING

[2] Adel Sedra, Kenneth C. Smith, Tony Chan Carusone, Vincent Gaudet, " Microelectronic Circuits", Oxford, 8th Ed. 2020 [3] Understanding Microelectronics: A Top-Down Approach by Franco Maloberti, Wiley (2011)

Reference Books: [1]. Analysis and Design of Analog Integrated Circuit, Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, John Wiley & Sons, Inc., 5th edition 2015 [2]. Analog MOS Integrated Circuits for Signal Processing, Roubik Gregorian, Gabor C. Temes, Wiley 1986 [3]. CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, Oxford University Press, 2nd edition, 2002. ISBN: 0-19-511644- [4]. Operational Amplifiers – Theory and Design, Johan H. Huijsing, Kluwer. ISBN: 0792372840 [5] CMOS: Circuit Design, Layout, and Simulation by R. Jacob Baker, Wiley-IEEE Press(2019) + Wiley SANSEN NPTEL / YouTube Lectures: Nagendra Krishnapura Analog Circuits, Analog IC Design, IITM Shanthi Pavan, Non-linear Circuits: IITM Tom Carusone : Microelectronic Circuits (Sedra & Smith Materials) David Jones. UoT https://www.eecg.utoronto.ca/~johns/ece331/ece331.html Nano : https://www.youtube.com/@ee292l

Misc: https://www.eecg.toronto.edu/~johns/ece331/videos/fabrication.mp

Mapping of CO (Course outcome), and PO (Programme Outcome) + PSO (Program Specific Outcome ) PO

CO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PSO

PSO

PSO

CO#1 3 2 3 2 2 3 1 1 1 1 1 1 3 2 2

CO#2^2 2 2 3 2 3 2 1 1 1 2 1 2 3

CO#3 3 2 2 2 3 2 2 1 1 1 1 1 2 3 2

CO#4 2 3 3 3 3 2 1 1 1 2 1 2 3 2 2

CO#5 2 2 2 3 2 3 2 1 1 1 2 1 2 3 3

CO#6 3 2 2 2 3 2 2 1 1 1 1 1 2 3 2

Correlation levels 1, 2 or 3 as defined below: 1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High)