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Material Type: Exam; Class: Computer Logic Design; Subject: Computer Design/Architecture; University: University of South Florida; Term: Unknown 1989;
Typology: Exams
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Test 2 Solutions CDA 3201 Fall 2003
You may have a copy of 1 2 3 4 5 6 total Table 6.3, p. 417 and Fig. 8.22, p. 522. 10 20 20 20 20 20 100
Please show complete work to receive full credit. Time = 75 minutes.
Present Next State, Z (output) State X = 0 X = 1 A B, 0 C, 1 B C, 0 D, 0 C D, 1 C, 1 D A, 1 B, 0
and an initial state of A, show the next states and Z (output) for the following X inputs
X input: 0 1 0 1 0 1 0 1 0 1 State: A B D A C D B C C D B Z (output): 0 0 1 1 1 0 0 1 1 0
Present Next State, Output Assignment State X = 0 X = 1 y1 y A A, 0 D, 0 0 0 B A, 0 C, 1 0 1 C C, 0 B, 1 1 1 D C, 0 A, 0 1 0
J1 = X K1 = X Y1 = X y1 + X y1 = X exc. or y
J2 = X y1 K2 = X y1 Y2 = X y2 + X y
Z = X y
Logic Diagram
State Table
Present Next State, Z State X = 0 X = 1 A A, 0 B, 0 B C, 0 B, 0 C D, 0 B, 0 D A, 0 B, 1
State Diagram
J1 = X K1 = X Y1 = X y1 + X y2 = X exc. or y
J2 = X y1 K2 = X y1 Y2 = X y1 + X y __ Z = X y
State Table
Present State, y1y2 Assignment Next State, Z X = 0 X = 1 A, 00 A, 0 D, 1 B, 01 A, 0 C, 0 C, 11 C, 0 B, 0 D, 10 C, 0 A, 1
State Diagram