timing analysis of digital design, Study notes of Digital Electronics

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It is all about Timing

Note: pictures in this lecture have been taken from various websites

A mandatory step in digital design process is the analysis, determination and elimination of possible timing violations within any design’s tolerance range. This fact is becoming more important for nano scale technology and the high speed requirements where greater density of today’s MCM, SOC, NoC and ASIC designs that are pushing the limits of speed. Any design must consider the fact that component timing varies from component to component chip to chip and board to board. Each chip/board that is manufactured contains a slightly different combination of fast and slow components that can cause some timing margin. The ASIC designer must always account for these variations and check timing violation if any within the ASIC chip and in the board that contains the ASIC using worse case corner analysis.

Timing Analysis

Timing....

A circuit board, MCM, SOC, ASIC … contain a variety of devices that cover the range of acceptable performance specifications. Naturally some devices will be fast and the others slow, but overall the circuit is expected to be within the specifications. Numerous factors can affect the performance of an ASIC/MCM/SOC/board such as the : Environment Factors: 1)Devices may be at different temperatures. Thus some devices will run faster than the others. 3)The layout affects the timing due to time constant of the routing area.

3. Process variation can cause the timing of each device to vary from typical specification. Many effects must be taken into account to ensure that the overall design is reliable and can be with high quality and meets its original specification.

Designed for the worst case

LOAD Condition

Delay and Timing Parameters Capacitances represent CMOS gate inputs Delay Equation Delay = [TP + K 1 ΣNi + KNi + K 2 ML ] K* TP = Intrinsic delay in (ns) K 1 = fan-out derating factor (ns / fan-out) ΣNi + KNi = Sum of input load being driven by the gate ( Equivalent unit loads) K 2 = Metal load derating factor (ns / μm) ML = Metal length being driven by the output ( μ m) K* = Composite derating factor due to process, temperature and voltage variation. IN OUT C_metal C_ gate

Path Timing

Tp

Input Loading Wirin g

Design checked before implementation

Example

In this example we will see how the fan-in and fan-out

contribute to delay and later we will show how environmental,

process, and voltage variation are incorporated in the

determination of the worst case delay estimation.

Determine the overall derating factor, K* for the following condition: ±10% voltage variation 40% process variation. (which are the factors contributing to the regions of ambiguity). Assume an ambient temperature of 25 °C. Power dissipation = 1W and chip and ceramic packaging has thermal resistance θJa=35 °C/W

Timing.. an example

Temperature Variation

Spatial and temporal temperature variation can

have drastic effects on signal propagation delay. In

CMOS, the variation in propagation delay due to

temperature is primarily because of the channel

current of the conducting device. Propagation

along a given path for CMOS network can be as

much as 50% slower at 125 °C then at room

temperature.

2. Voltage The delay increases inversely with voltage: td α 1/Vdd let fv be defined as the voltage variation factor then: tdv = kv td where tdv, is the delay with voltage variation for ± 10% variation on a 1volt supply fv= ± 10% kv = (1 ± 0.01 fv)

= (1 ± 0.1 )

= 1 / 0. = 1.11 or 11% increase

Timing....[ voltage ]

Chain propagation (ms) – 50 inverters 9 8 7 6 5 4 1 2 3 4 5 6 (^7) Process fabrication run number Process Propagation Delay Fast 14. Slow 21 Typical 18. Usually from +20 % to –20 % fluctuation i.e. 40% change Process parameters are characterized as nominal and corner:  (^) The nominal process is the expected process.  (^) Corner processes are the limits of acceptable process parameters.

Process

Variations

Timing....[ different gates ]

Apart from external variables discussed, the data dependent delay results from two effects:

1. In CMOS circuits type of the gate used and the number of the inputs is a factor i.e. 2 or 3-input NAND or NOR will have different delay sensitivities. This is why when designs are done with one type like 2-input NAND/INV. The delay variation is more predictable.
2. Signal propagation does not generally occur from a single input to a given output along one path. There are transitions occurring along multiple paths interacting with each other from any number of inputs to the given output. Both of these data dependent delays can be minimized by design. Path length variations and data dependencies are in turn dependent upon logic function implementation.

Determine the delay experienced by the driver circuit given below with a nominal delay of Tp=1.5 ps. This is a very much simplified delay calculation to show the effects of the routing and fanout Assume 1UL(unit load) for basic inverter or 2-input NAND value e.g. 5fF D D D Tp=1.5 ns L=2.5mm 2UL 2UL 2UL D 1UL 2UL

Example

1UL …14 UL Combined load Lets assume the following 2 constants: K1= 0.06 ns/UL delay factor per unit load connected K2= 0.08 ns/mm delay factor per unit length wire

Worst Case Timing Analysis Worst case timing analysis involves determining the regions of ambiguity , or the range of time in which a state strength may change. Standard representation of the ambiguity region is by a series of signal edges close together or with a timing envelope. The beginning and end of the ambiguity region are measured with respect to a referenced event such as the clock. The diagram below shows the earliest and the latest time at which the specified signal makes the transition for ‘0’ to ‘1’. Rising signal ambiguity Envelope

Timing Analysis........ ambiguity regions

Earliest arriving signal Latest arriving signal

20 If several combinational logic elements are connected serially, the ambiguity region can grow quite large, and in fact this accurately represents the results of the several worst cases combined. The case when all the components have minimum delay, and the case when all have maximum delay. 4 8 8 16 12 24 Min Max A D-type flip flop can reduce the ambiguity of a signal on its input and this is a major reason for using synchronous elements in a design. Any accumulated ambiguity on the D input is eliminated and is replaced with the combined ambiguity of the CLK input and the output. D 50 55 60

Timing Analysis....

Delay CLK to

5 50