VLSI Design: Understanding Delay, Arrival Time, and RC Model in Digital Circuit Design, Lab Reports of Very large scale integration (VLSI)

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UNIT III

• Delay

• Combinational Circuit Design

Delay

• IC : Working Chip – perform intended function
• Making working chip “work well”:
  • Performance metrics: Speed (delay), Power

Contamination Delay

It is the amount

of time needed

for change in a

logic input to

result in an

initial change at

an output

Arrival Time Example

• If the outputs are all required at 200 ps, the circuit has 60 ps of slack.
• The timing analyzer use the arrival time model to verify that setup and hold

times are satisfied at each register

RC Model

• MOSFETs exhibits non-linear I V characteristics. (Recall ID expressions for long-channel device), analysis is complex and tedious.
• Solution: Develop linear model of the MOSFET

RC-Model (Contd.)

• Rn=1/βn (VDD—Vtn)
• βn = μn Cox (W/L)
• The value of Rn depends on the device aspect ratio, (W/L): Increase in W decrease Rn

RC-Model (Contd.)

Cs = CGS + CSB CD = CGD + CDB The value of CS and CD depends on the device aspect ratio, (W/L)

CGS= CGD= CG/

= [Cox (WxL)]/

Transient Response: Inverter