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Timer
General Description
The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external re- sistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or drive TTL circuits.
Features
n Direct replacement for SE555/NE n Timing from microseconds through hours n Operates in both astable and monostable modes n Adjustable duty cycle n Output can source or sink 200 mA n Output and supply TTL compatible n Temperature stability better than 0.005% per ˚C n Normally on and normally off output n Available in 8-pin MSOP package
Applications
n Precision timing n Pulse generation n Sequential timing n Time delay generation n Pulse width modulation n Pulse position modulation n Linear ramp generator
Schematic Diagram
DS007851-
February 2000
LM555 Timer
© 2000 National Semiconductor Corporation DS007851 www.national.com
Connection Diagram
Ordering Information
Package Part Number Package Marking Media Transport NSC Drawing 8-Pin SOIC LM555CM LM555CM Rails M08A LM555CMX LM555CM 2.5k Units Tape and Reel 8-Pin MSOP LM555CMM Z55 1k Units Tape and Reel MUA08A LM555CMMX Z55 3.5k Units Tape and Reel 8-Pin MDIP LM555CN LM555CN Rails N08E
Dual-In-Line, Small Outline and Molded Mini Small Outline Packages
DS007851- Top View
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Electrical Characteristics (Notes 1, 2) (Continued)
(T (^) A = 25˚C, V (^) CC = +5V to +15V, unless othewise specified) Parameter Conditions Limits Units LM555C Min Typ Max Output Voltage Drop (Low) VCC = 15V ISINK = 10mA 0.1 0.25 V I (^) SINK = 50mA 0.4 0.75 V I (^) SINK = 100mA 2 2.5 V I (^) SINK = 200mA 2.5 V V (^) CC = 5V ISINK = 8mA V I (^) SINK = 5mA 0.25 0.35 V Output Voltage Drop (High) ISOURCE = 200mA, V (^) CC = 15V 12.5 V ISOURCE = 100mA, V (^) CC = 15V 12.75 13.3 V VCC = 5V 2.75 3.3 V Rise Time of Output 100 ns Fall Time of Output 100 ns Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func- tional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar- antee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: For operating at elevated temperatures the device must be derated above 25˚C based on a +150˚C maximum junction temperature and a thermal resistance of 106˚C/W (DIP), 170˚C/W (S0-8), and 204˚C/W (MSOP) junction to ambient. Note 4: Supply current when output high typically 1 mA less at V (^) CC = 5V. Note 5: Tested at VCC = 5V and VCC = 15V. Note 6: This will determine the maximum value of R (^) A + RB for 15V operation. The maximum total (R (^) A + RB ) is 20MΩ. Note 7: No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded. Note 8: Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.
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Typical Performance Characteristics
Minimuim Pulse Width Required for Triggering
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Supply Current vs. Supply Voltage
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High Output Voltage vs. Output Source Current
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Low Output Voltage vs. Output Sink Current
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Low Output Voltage vs. Output Sink Current
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Low Output Voltage vs. Output Sink Current
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Applications Information
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot
(Figure 1). The external capacitor is initially held discharged
by a transistor inside the timer. Upon application of a nega- tive trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.
The voltage across the capacitor then increases exponen- tially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the
output to its low state.Figure 2 shows the waveforms gener-
ated in this mode of operation. Since the charge and the threshold level of the comparator are both directly propor- tional to supply voltage, the timing internal is independent of supply.
During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10μs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied.
When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false trig- gering.
Figure 3 is a nomograph for easy determination of R, C val-
ues for various time delays.
NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle.
ASTABLE OPERATION
If the circuit is connected as shown inFigure 4 (pins 2 and 6
connected) it will trigger itself and free run as a multivibrator. The external capacitor charges through RA + RB and dis- charges through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors.
In this mode of operation, the capacitor charges and dis- charges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore the fre- quency are independent of the supply voltage.
DS007851- FIGURE 1. Monostable
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V (^) CC = 5V Top Trace: Input 5V/Div. TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div. RA = 9.1kΩ Bottom Trace: Capacitor Voltage 2V/Div. C = 0.01μF
FIGURE 2. Monostable Waveforms
DS007851- FIGURE 3. Time Delay
DS007851- FIGURE 4. Astable
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Applications Information (Continued)
Figure 5 shows the waveforms generated in this mode of
operation.
The charge time (output high) is given by: t 1 = 0.693 (R (^) A + RB ) C And the discharge time (output low) by: t 2 = 0.693 (R (^) B ) C Thus the total period is: T = t 1 + t 2 = 0.693 (R (^) A +2RB ) C The frequency of oscillation is:
Figure 6 may be used for quick determination of these RC
values. The duty cycle is:
FREQUENCY DIVIDER
The monostable circuit ofFigure 1 can be used as a fre-
quency divider by adjusting the length of the timing cycle.
Figure 7 shows the waveforms generated in a divide by three
circuit.
PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to pin 5.Figure
8 shows the circuit, and inFigure 9 are some waveform
examples.
DS007851- V (^) CC = 5V Top Trace: Output 5V/Div. TIME = 20μs/DIV. Bottom Trace: Capacitor Voltage 1V/Div. RA = 3.9kΩ R (^) B = 3kΩ C = 0.01μF FIGURE 5. Astable Waveforms
DS007851- FIGURE 6. Free Running Frequency
DS007851- V (^) CC = 5V Top Trace: Input 4V/Div. TIME = 20μs/DIV. Middle Trace: Output 2V/Div. RA = 9.1kΩ Bottom Trace: Capacitor 2V/Div. C = 0.01μF FIGURE 7. Frequency Divider
DS007851- FIGURE 8. Pulse Width Modulator
DS007851- V (^) CC = 5V Top Trace: Modulation 1V/Div. TIME = 0.2 ms/DIV. Bottom Trace: Output Voltage 2V/Div. RA = 9.1kΩ C = 0.01μF FIGURE 9. Pulse Width Modulator
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Applications Information (Continued)
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors RA and RB may be con-
nected as inFigure 14. The time period for the output high is
the same as previous, t 1 = 0.693 R (^) A C. For the output low it is t 2 =
Thus the frequency of oscillation is
Note that this circuit will not oscillate if RB is greater than 1/ RA because the junction of R (^) A and R (^) B cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator.
ADDITIONAL INFORMATION Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1μF in par- allel with 1μF electrolytic. Lower comparator storage time can be as long as 10μs when pin 2 is driven fully to ground for triggering. This limits the monostable pulse width to 10μs minimum. Delay time reset to output is 0.47μs typical. Minimum reset pulse width must be 0.3μs, typical. Pin 7 current switches within 30ns of the output (pin 3) volt- age.
DS007851- FIGURE 14. 50% Duty Cycle Oscillator
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Physical Dimensions inches (millimeters) unless otherwise noted
Small Outline Package (M) NS Package Number M08A
8-Lead (0.118” Wide) Molded Mini Small Outline Package NS Package Number MUA08A
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